Asynchronous systems—much like object-oriented software—are typically constructed out of modular ‘hardware objects’, each with well-defined communication interfaces. For example, in the design of processing cores, it is often common to combine several processing components and to interface these components with shared resources. Examples of the type of resources that can be shared between processing components include for example instruction (cache) memory, data (cache) memory and advanced computation components (e.g. floating point computation units). The interfacing between modules creates challenges in the sense that setup and hold violation, metastability and unreliable data transfers may occur since the components of the system are independently designed.
A first approach for interfacing components is commonly referred to as the handshaking protocol. A simple channel used to perform handshaking between two components typically consists of two wires: a request wire and an acknowledge wire. Different variations of the handshaking approach have been suggested, all requiring some type of exchange of request and acknowledgement messages between the components being interfaced in order to complete a transaction between these components. Handshaking approaches are well-known in the art and as such will not be described in further detail here.
A deficiency with the use of handshaking approaches for synchronization purposes is that they incur delays over and above the time required to complete a transaction between two components.
A second approach for interfacing systems is the use of an asynchronous first-in-first-out (FIFO) approach. FIFOs are used commonly in electronic circuits for buffering and flow control. In hardware form, a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. An asynchronous FIFO has two interfaces, one for writing the data into the FIFO and the other for reading the data out and makes use of different signals for reading and writing. Asynchronous FIFO approaches are well-known in the art and as such will not be describe in further detail here.
A deficiency with the use of asynchronous FIFO approaches for synchronization purposes is that they require significant additional system resources for both the implementation of the FIFO itself as well as for the various control signals used for reading from and writing to the FIFO and to indicate the full/empty state of the FIFO.
Difficulties associated with interfacing components using either a handshaking approach or a FIFO approach are compounded in circumstance where “resource” components (or “slave” components) are shared amongst several “processing” components (or “master” components).
In the context of the above, there is a need to provide a method and associated circuit for interfacing components that alleviates at least in part problems associated with existing approaches.